View CY14E064L-SZ25XC_4253417.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

CY14E064L
64 Kbit (8K x 8) nvSRAM
Features

Functional Description
The Cypress CY14E064L is a fast static RAM with a non-volatile element in each memory cell. The embedded non-volatile elements incorporate QuantumTrap technology producing the world's most reliable non-volatile memory. The SRAM provides unlimited read and write cycles, while independent, non-volatile data resides in the highly reliable QuantumTrap cell. Data transfers from the SRAM to the non-volatile elements (the STORE operation) takes place automatically at power down. On power up, data is restored to the SRAM (the RECALL operation) from the non-volatile memory. Both the STORE and RECALL operations are also available under software control. A hardware STORE is initiated with the HSB pin.
25 ns and 45 ns access times Hands off automatic STORE on power down with external 68 mF capacitor STORE to QuantumTrap(R) non-volatile elements is initiated by software, hardware or AutoStore on power down RECALL to SRAM initiated by software or power up Unlimited READ, WRITE and RECALL cycles 10 mA typical ICC at 200 ns cycle time 1,000,000 STORE cycles to QuantumTrap 100 year data retention to QuantumTrap Single 5V operation +10% Commercial temperature SOIC package RoHS compliance
Logic Block Diagram
Quantum Trap 128 X 512 STORE
V CC
V CAP
A5
A7 A8 A9 A 11 A 12
ROW DECODER
A6
POWER CONTROL STORE/ RECALL CONTROL
STATIC RAM ARRAY 128 X 512
RECALL
HSB
SOFTWARE DETECT COLUMN I/O
A0
- A12
DQ 0 DQ 2 DQ 3 DQ 4 DQ 5 DQ 6 DQ 7
INPUT BUFFERS
DQ 1
COLUMN DEC
A 0 A 1 A 2 A 3 A 4 A 10
OE
CE WE
Cypress Semiconductor Corporation Document Number: 001-06543 Rev. *D
*
198 Champion Court
*
San Jose, CA 95134-1709
* 408-943-2600 Revised August 7, 2007
[+] Feedback
CY14E064L
Pin Configurations
V CAP A 12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 V SS
1 2 3 4 5 6 7 8 9 10 11 12 13 14
V CC WE HSB A8
28-SOIC
Top View
(Not To Scale)
A9 A 11 OE A 10 CE DQ7 DQ6 DQ5 DQ4 DQ3
Pin Definitions
Pin Name A0-A12 WE CE OE VSS VCC HSB IO Type Input Input Input Input Ground Power Supply Description Address Inputs. Used to select one of the 8,192 bytes of the nvSRAM. Write Enable Input, Active LOW. When selected LOW, writes data on the IO pins to the address location latched by the falling edge of CE. Chip Enable Input, Active LOW. When LOW, selects the chip. When HIGH, deselects the chip. Output Enable, Active LOW. The active LOW OE input enables the data output buffers during read cycles. Deasserting OE HIGH causes the IO pins to tri-state. Ground for the Device. The device is connected to ground of the system. Power Supply Inputs to the Device.
DQ0-DQ7 Input or Output Bidirectional Data IO lines. Used as input or output lines depending on operation.
Input or Output Hardware Store Busy (HSB). When LOW, this output indicates a Hardware Store is in progress. When pulled low external to the chip, it initiates a non-volatile STORE operation. A weak internal pull up resistor keeps this pin high if not connected (connection optional). Power Supply AutoStore Capacitor. Supplies power to nvSRAM during power loss to store data from SRAM to non-volatile elements.
VCAP
Document Number: 001-06543 Rev. *D
Page 2 of 17
[+] Feedback
CY14E064L
Device Operation
The CY14E064L nvSRAM is made up of two functional components paired in the same physical cell. These are an SRAM memory cell and a non-volatile QuantumTrap cell. The SRAM memory cell operates as a standard fast static RAM. Data in the SRAM is transferred to the non-volatile cell (the STORE operation) or from the non-volatile cell to SRAM (the RECALL operation). This unique architecture enables the storage and recall of all cells in parallel. During the STORE and RECALL operations, SRAM READ and WRITE operations are inhibited. The CY14E064L supports unlimited reads and writes similar to a typical SRAM. In addition, it provides unlimited RECALL operations from the non-volatile cells and up to one million STORE operations.
1. Hardware store activated by HSB 2. Software store activated by an address sequence 3. AutoStore on device power down AutoStore operation is a unique feature of QuantumTrap technology and is enabled by default on the CY14E064L. During normal operation, the device draws current from VCC to charge a capacitor connected to the VCAP pin. This stored charge is used by the chip to perform a single STORE operation. If the voltage on the VCC pin drops below VSWITCH, the part automatically disconnects the VCAP pin from VCC. A STORE operation is initiated with power provided by the VCAP capacitor. Figure 1 shows the proper connection of the storage capacitor (VCAP) for automatic store operation. Refer to the "DC Electrical Characteristics" on page 7 for the size of VCAP. The voltage on the VCAP pin is driven to 5V by a charge pump internal to the chip. A pull up is placed on WE to hold it inactive during power up. Figure 1. AutoStore Mode
SRAM Read
The CY14E064L performs a READ cycle whenever CE and OE are LOW while WE and HSB are HIGH. The address specified on pins A0-12 determines the 8,192 data bytes accessed. When the READ is initiated by an address transition, the outputs are valid after a delay of tAA (READ cycle 1). If the READ is initiated by CE or OE, the outputs are valid at tACE or at tDOE, whichever is later (READ cycle 2). The data outputs repeatedly respond to address changes within the tAA access time without the need for transitions on any control input pins, and remains valid until another address change or until CE or OE is brought HIGH, or WE or HSB is brought LOW.
10k Ohm
1
28 27 26
SRAM Write
A WRITE cycle is performed whenever CE and WE are LOW and HSB is HIGH. The address inputs are stable prior to entering the WRITE cycle and must remain stable until either CE or WE goes HIGH at the end of the cycle. The data on the common IO pins I/O0-7 are written into the memory if it is valid tSD, before the end of a WE controlled WRITE or before the end of an CE controlled WRITE. Keep OE HIGH during the entire WRITE cycle to avoid data bus contention on common IO lines. If OE is left LOW, internal circuitry turns off the output buffers tHZWE after WE goes LOW.
68 UF 6v, +20%
U 0.1 F Bypass
AutoStore Operation
The CY14E064L stores data to nvSRAM using one of three storage operations:
14
15
Document Number: 001-06543 Rev. *D
10k Ohm
Page 3 of 17
[+] Feedback
CY14E064L
In system power mode, both VCC and VCAP are connected to the +5V power supply without the 68 F capacitor. In this mode, the AutoStore function of the CY14E064L operates on the stored system charge as power goes down. The user must, however, guarantee that VCC does not drop below 3.6V during the 10 ms STORE cycle. If an automatic STORE on power loss is not required, then VCC is tied to ground and + 5V is applied to VCAP (Figure 2). This is the AutoStore Inhibit mode, where the AutoStore function is disabled. If the CY14E064L is operated in this configuration, references to VCC are changed to VCAP throughout this datasheet. In this mode, STORE operations are triggered through software control or the HSB pin. It is not permissible to change between these three options at will. To reduce Figure 2. AutoStore Inhibit Mode
0.1U F Bypass
place. If a WRITE is in progress when HSB is pulled LOW, it allows a time, tDELAY to complete. However, any SRAM WRITE cycles requested after HSB goes LOW are inhibited until HSB returns HIGH. The HSB pin is used to synchronize multiple CY14E064L while using a single larger capacitor. To operate in this mode, the HSB pin is connected together to the HSB pins from the other CY14E064L. An external pull up resistor to +5V is required, since HSB acts as an open drain pull down. The VCAP pins from the other CY14E064L parts are tied together and share a single capacitor. The capacitor size is scaled by the number of devices connected to it. When any one of the CY14E064L detects a power loss and asserts HSB, the common HSB pin causes all parts to request a STORE cycle. (A STORE takes place in those CY14E064L that are written since the last non-volatile cycle.) During any STORE operation, regardless of how it is initiated, the CY14E064L continues to drive the HSB pin LOW, releasing it only when the STORE is complete. After completing the STORE operation, the CY14E064L remains disabled until the HSB pin returns HIGH. If HSB is not used, it is left unconnected.
10k Ohm
1
28 27 26
10k Ohm
Hardware RECALL (Power Up)
During power up or after any low power condition (VCC < VSWITCH), an internal RECALL request is latched. When VCC once again exceeds the sense voltage of VSWITCH, a RECALL cycle is automatically initiated and takes tHRECALL to complete. If the CY14E064L is in a WRITE state at the end of power up RECALL, the SRAM data is corrupted. To help avoid this situation, a 10 Kohm resistor is connected either between WE and system VCC or between CE and system VCC.
Software STORE
14 15
unnecessary non-volatile stores, AutoStore and Hardware Store operations are ignored, unless at least one WRITE operation has taken place since the most recent STORE or RECALL cycle. Software initiated STORE cycles are performed regardless of whether a WRITE operation has taken place. The HSB signal is monitored by the system to detect if an AutoStore cycle is in progress.
Using a software address sequence, transfer the data from the SRAM to the non-volatile memory. The CY14E064L software STORE cycle is initiated by executing sequential CE controlled READ cycles from six specific address locations in exact order. During the STORE cycle, an erase of the previous non-volatile data is first performed followed by a program of the non-volatile elements. Once a STORE cycle is initiated, further input and output are disabled until the cycle is completed. Because a sequence of READs from specific addresses is used for STORE initiation, it is important that no other READ or WRITE accesses intervene in the sequence. If they intervene, the sequence is aborted and no STORE or RECALL takes place. To initiate the software STORE cycle, the following READ sequence is performed: 1. Read address 0x0000, Valid READ 2. Read address 0x1555, Valid READ 3. Read address 0x0AAA, Valid READ 4. Read address 0x1FFF, Valid READ 5. Read address 0x10F0, Valid READ 6. Read address 0x0F0F, Initiate STORE cycle The software sequence is clocked with CE controlled READs or OE controlled READs. Once the sixth address in the sequence is entered, the STORE cycle commences and the Page 4 of 17
Hardware STORE (HSB) Operation
The CY14E064L provides the HSB pin for controlling and acknowledging the STORE operations. The HSB pin is used to request a hardware STORE cycle. When the HSB pin is driven LOW, the CY14E064L conditionally initiates a STORE operation after tDELAY. An actual STORE cycle only begins if a WRITE to the SRAM takes place since the last STORE or RECALL cycle. The HSB pin also acts as an open drain driver that is internally driven LOW to indicate a busy condition, while the STORE (initiated by any means) is in progress. SRAM READ and WRITE operations, that are in progress when HSB is driven LOW by any means, are given time to complete before the STORE operation is initiated. After HSB goes LOW, the CY14E064L continues SRAM operations for tDELAY. During tDELAY, multiple SRAM READ operations take Document Number: 001-06543 Rev. *D
[+] Feedback
CY14E064L
chip is disabled. It is important that READ cycles and not WRITE cycles are used in the sequence. It is not necessary that OE is LOW for a valid sequence. After the tSTORE cycle time is fulfilled, the SRAM is again activated for READ and WRITE operation.
Low Average Active Power
CMOS technology provides the CY14E064L the benefit of drawing significantly less current when it is cycled at times longer than 50 ns. Figure 3 shows the relationship between ICC and READ or WRITE cycle time. Worst case current consumption is shown for both CMOS and TTL input levels (commercial temperature range, VCC = 5.5V, 100% duty cycle on chip enable). Only standby current is drawn when the chip is disabled. The overall average current drawn by the CY14E064L depends on the following items: 1. The duty cycle of chip enable 2. The overall cycle rate for accesses 3. The ratio of READs to WRITEs 4. CMOS versus TTL input levels 5. The operating temperature 6. The VCC level 7. IO loading Figure 3. Current Versus Cycle Time (READ)
Software RECALL
Data is transferred from the non-volatile memory to the SRAM by a software address sequence. A software RECALL cycle is initiated with a sequence of READ operations in a manner similar to the software STORE initiation. To initiate the RECALL cycle, the following sequence of CE controlled READ operations is performed: 1. Read address 0x0000, Valid READ 2. Read address 0x1555, Valid READ 3. Read address 0x0AAA, Valid READ 4. Read address 0x1FFF, Valid READ 5. Read address 0x10F0, Valid READ 6. Read address 0x0F0E, Initiate RECALL cycle Internally, RECALL is a two step procedure. First, the SRAM data is cleared, and then the non-volatile information is transferred into the SRAM cells. After the tRECALL cycle time, the SRAM is once again ready for READ and WRITE operations. The RECALL operation does not alter the data in the non-volatile elements.
Data Protection
The CY14E064L protects data from corruption during low voltage conditions by inhibiting all externally initiated STORE and WRITE operations. The low voltage condition is detected when VCC is less than VSWITCH. If the CY14E064L is in a WRITE mode (both CE and WE are low) at power up after a RECALL or after a STORE, the WRITE is inhibited until a negative transition on CE or WE is detected. This protects against inadvertent writes during power up or brown out conditions.
Noise Considerations
The CY14E064L is a high speed memory. It must have a high frequency bypass capacitor of approximately 0.1 F connected between VCC and VSS, using leads and traces that are as short as possible. As with all high speed CMOS ICs, careful routing of power, ground, and signals reduce circuit noise.
Figure 4. Current Versus Cycle Time (WRITE)
Document Number: 001-06543 Rev. *D
Page 5 of 17
[+] Feedback
CY14E064L
Preventing STOREs
The STORE function is disabled by holding HSB high with a driver capable of sourcing 30 mA at a VOH of at least 2.2V, because it has to overpower the internal pull down device. This device drives HSB LOW for 20 s at the onset of a STORE. Table 1. Hardware Mode Selection CE H L L X L WE X H L X H HSB H H H L H A12-A0 X X X X 0000 1555 0AAA 1FFF 10F0 0F0F 0000 1555 0AAA 1FFF 10F0 0F0E Mode Not Selected Read SRAM Write SRAM Non-volatile STORE Read SRAM Read SRAM Read SRAM Read SRAM Read SRAM Non-volatile STORE Read SRAM Read SRAM Read SRAM Read SRAM Read SRAM Non-volatile RECALL IO Output High Z Output Data Input Data Output High Z Output Data Output Data Output Data Output Data Output Data Output High Z Output Data Output Data Output Data Output Data Output Data Output High Z Power Standby Active Active ICC2 Active ICC2 When the CY14E064L is connected for AutoStore operation (system VCC connected to VCC and a 68 F capacitor on VCAP) and VCC crosses VSWITCH on the way down, the CY14E064L attempts to pull HSB LOW. If HSB does not actually get below VIL, the part stops trying to pull HSB LOW and abort the STORE attempt.
L
H
H
Active
Document Number: 001-06543 Rev. *D
Page 6 of 17
[+] Feedback
CY14E064L
Maximum Ratings
Exceeding maximum ratings may shorten the useful life of the device. These user guidelines are not tested. Storage Temperature ................................. -65C to +150C Ambient Temperature with Power Applied ............................................ -55C to +125C Supply Voltage on VCC Relative to GND ..........-0.5V to 7.0V Voltage Applied to Outputs in High Z State ....................................... -0.5V to VCC + 0.5V Input Voltage.............................................-0.5V to Vcc+0.5V
Transient Voltage (<20 ns) on Any Pin to Ground Potential .................. -2.0V to VCC + 2.0V Package Power Dissipation Capability (TA = 25C) ................................................... 1.0W Surface Mount Lead Soldering Temperature (3 Seconds) .......................................... +260C Output Short Circuit Current [1] .................................... 15 mA Static Discharge Voltage.......................................... > 2001V (MIL-STD-883, Method 3015) Latch up Current.................................................... > 200 mA
Operating Range
Range Commercial Ambient Temperature 0C to +70C VCC 4.5V to 5.5V
DC Electrical Characteristics
Parameter ICC1 Description Average VCC Current
Over the operating range (VCC = 4.5V to 5.5V) [2] Test Conditions tRC = 25 ns Commercial tRC = 45 ns Dependent on output loading and cycle rate. Values obtained without output loads. IOUT = 0mA. All Inputs Do Not Care, VCC = Max Average current for duration tSTORE WE > (VCC - 0.2). All other inputs cycling. Dependent on output loading and cycle rate. Values obtained without output loads. Min Max 85 65 Unit mA mA
ICC2 ICC3
Average VCC Current during STORE Average VCC Current at tAVAV = 200 ns, 5V, 25C Typical
3 10
mA mA
ICC4 ISB
Average VCAP Current All Inputs Do Not Care, VCC = Max during AutoStore Cycle Average current for duration tSTORE VCC Standby Current CE > (VCC - 0.2). All others VIN < 0.2V or > (VCC - 0.2V). Standby current level after non-volatile cycle is complete. Inputs are static. f = 0MHz. -1 -5 2.2 VSS - 0.5 IOUT = -2 mA IOUT = 4 mA 2.4 VCC = Max, VSS < VIN < VCC, CE or OE > VIH
2 2.5
mA mA
IIX IOZ VIH VIL VOH VOL
Input Leakage Current VCC = Max, VSS < VIN < VCC Off State Output Leakage Current Input HIGH Voltage Input LOW Voltage Output HIGH Voltage Output LOW Voltage
+1 +5 VCC + 0.5 0.8 0.4
A A V V V V
Note 1. Outputs shorted for no more than one second. No more than one output shorted at a time. 2. Typical conditions for the active current shown on the front page of the datasheet are average values at 25C (room temperature) and VCC = 5V. Not 100% tested.
Document Number: 001-06543 Rev. *D
Page 7 of 17
[+] Feedback
CY14E064L
Capacitance
These parameters are guaranteed but not tested. Parameter CIN COUT Description Input Capacitance Output Capacitance Test Conditions TA = 25C, f = 1 MHz, VCC = 0 to 3.0 V Max 8 7 Unit pF pF
Thermal Resistance
[
These parameters are guaranteed but not tested. Parameter Description Test Conditions 28-SOIC TBD TBD Unit C/W C/W
JA JC
Thermal Resistance Test conditions follow standard test methods and procedures (Junction to Ambient) for measuring thermal impedance, per EIA / JESD51. Thermal Resistance (Junction to Case)
AC Test Loads
R1 963W 5.0V Output 30 pF R2 512 Output 5 pF R2 512 5.0V R1 963 For Tri-state Specs
AC Test Conditions
Input Pulse Levels .................................................. 0 V to 3 V Input Rise and Fall Times (10% - 90%)........................ <5 ns Input and Output Timing Reference Levels ................... 1.5 V
Document Number: 001-06543 Rev. *D
Page 8 of 17
[+] Feedback
CY14E064L
AC Switching Characteristics
Parameter Cypress Parameter tACE tRC tAA
[4] [5]
25 ns Part Description Min Max
45 ns Part Min Max Unit
Alt.
SRAM Read Cycle tACS tRC tAA tOE tOH tLZ tHZ tOLZ tOHZ tPA tPS tWC tWP tCW tDW tDH tAW tAS tWR tWZ tOW
[6] [6] [6]
Chip Enable Access Time Read Cycle Time Address Access Time Output Enable to Data Valid Output Hold After Address Change Chip Enable to Output Active Chip Disable to Output Inactive Output Enable to Output Active Output Disable to Output Inactive Chip Enable to Power Active Chip Disable to Power Standby Write Cycle Time Write Pulse Width Chip Enable To End of Write Data Setup to End of Write Data Hold After End of Write Address Setup to End of Write Address Setup to Start of Write Address Hold After End of Write Write Enable to Output Disable Output Active After End of Write 5 25 20 20 10 0 20 0 0 0 0 5 5 25
25 45 25 10 5 5 10 0 10 0 25 45 30 30 15 0 30 0 0 10 5
45 45 20
ns ns ns ns ns ns
tDOE tOHA [5] tLZCE tHZCE
12 12 45
ns ns ns ns ns ns ns ns ns ns ns ns ns
tLZOE [6] tHZOE [6] tPU tPD tWC tPWE tSCE tSD tHD tAW tSA tHA tHZWE [6,7] tLZWE
[3] [3]
SRAM Write Cycle
14
ns ns
AutoStore/Power Up RECALL
Parameter tHRECALL [8] tSTORE
[9]
Description Power up RECALL Duration STORE Cycle Duration Low Voltage Trigger Level VCC Rise Time
CY14E064L Min Max 550 10 4.0 150 4.5
Unit s ms V s
VSWITCH tVCCRISE
Notes 3. These parameters are guaranteed but not tested. 4. WE must be HIGH during SRAM Read Cycles. 5. Device is continuously selected with CE and OE both Low. 6. Measured 200mV from steady state output voltage. 7. If WE is Low when CE goes Low, the outputs remain in the high impedance state. 8. tHRECALL starts from the time VCC rises above VSWITCH. 9. If an SRAM Write does not take place since the last non-volatile cycle, no STORE takes place.
Document Number: 001-06543 Rev. *D
Page 9 of 17
[+] Feedback
CY14E064L
Software Controlled STORE/RECALL Cycle
The software controlled STORE/RECALL cycle follows. [10,11] Parameter tRC tAS tCW tGLAX tRECALL Description STORE/RECALL Initiation Cycle Time Address Setup Time Clock Pulse Width Address Hold Time RECALL Duration 25 ns Part Min 25 0 20 20 20 Max 45 ns Part Min 45 0 30 20 20 Max Unit ns ns ns ns s
Hardware STORE Cycle
Parameter tSTORE [6] tDELAY [12] tRESTORE tHLHX tHLBL
[13]
Description STORE Cycle Duration Time Allowed to Complete SRAM Cycle Hardware STORE High to Inhibit Off Hardware STORE Pulse Width Hardware STORE Low to STORE Busy
CY14E064L Min 1 700 15 300 Max 10
Unit ms s ns ns ns
Notes 10. The software sequence is clocked with CE controlled READs. 11. The six consecutive addresses must be read in the order listed in the Mode Selection table. WE must be HIGH during all six consecutive cycles. 12. Read and Write cycles in progress before HSB are given this amount of time to complete. 13. tRESTOREis only applicable after tSTORE is complete.
Document Number: 001-06543 Rev. *D
Page 10 of 17
[+] Feedback
CY14E064L
Switching Waveforms
Figure 5. SRAM Read Cycle 1: Address Controlled [4, 5, 14]
tRC
ADDRESS
t AA t OH
DQ (DATA OUT) DATA VALID
Figure 6. SRAM Read Cycle 2: CE Controlled [4,14]
t RC
ADDRESS
CE
tLZCE
t ACE
t PD tHZCE
OE
DQ (DATA OUT)
t LZOE t PU
tDOE
DATA VALID
tHZOE
ACTIVE
ICC
STANDBY
Note 14. HSB must remain HIGH during READ and WRITE cycles.
Document Number: 001-06543 Rev. *D
Page 11 of 17
[+] Feedback
CY14E064L
Switching Waveforms (continued)
Figure 7. SRAM Write Cycle 1: WE Controlled [14,15]
tWC
ADDRESS
tSCE
CE
tHA
tAW tSA
WE
tPWE tSD tHD
DATA IN
DATA VALID
tHZWE
DATA OUT PREVIOUS DATA
HIGH IMPEDANCE
tLZWE
Figure 8. SRAM Write Cycle 2: CE Controlled
tWC
ADDRESS
CE
tSA tAW tPWE
tSCE
tHA
WE
tSD
DATA IN DATA VALID
tHD
Note 15. CE or WE must be greater than VIH during address transitions.
Document Number: 001-06543 Rev. *D
Page 12 of 17
[+] Feedback
CY14E064L
Switching Waveforms (continued)
Figure 9. AutoStore/Power Up RECALL
V CC V SWITCH V RESET
AutoStore
POWER-UP RECALL
tRESTORE
HSB
tVSBL tDELAY
tSTORE
DQ (DATA OUT)
POWER UP RECALL
(NO SRAM WRITES)
BROWN OUT NO STROKE
BROWN OUT AutoStore TM NO RECALL (VCC DID NOT GO BELOW VRESET)
BROWN OUT AutoStore TM RECALL WHEN VCC RETURNS ABOVE VSWITCH
NO RECALL (VCC DID NOT GO BELOW VRESET)
Document Number: 001-06543 Rev. *D
Page 13 of 17
[+] Feedback
CY14E064L
Switching Waveforms (continued)
Figure 10. CE Controlled Software STORE/RECALL Cycle [9]
tRC
ADDRESS ADDRESS # 1
tRC
ADDRESS # 6
tSA
CE
tSCE
tGLAX
OE
t STORE / t RECALL
DQ (DATA) DATA VALID DATA VALID
HIGH IMPEDANCE
Figure 11. Hardware STORE Cycle
HSB (IN)
tHLHX tSTORE
HIGH IMPEDANCE
HSB (OUT)
tHLBL
HIGH IMPEDANCE
t DELAY
DQ (DATA OUT) DATA VALID DATA VALID
Document Number: 001-06543 Rev. *D
Page 14 of 17
[+] Feedback
CY14E064L
Part Numbering Nomenclature CY 14 E 064 L- SZ 25 X C T
Option: T-Tape and Reel Blank - Std. Temperature: C - Commercial (0 to 70C) Pb-Free Package: SZ - 28-SOIC Data Bus: L - x8 Speed: 25 - 25 ns 45 - 45 ns
Density: 064 - 64 Kb
Voltage: E - 5.0V nvSRAM 14 - AutoStore + Software Store + Hardware Store
Cypress
Document Number: 001-06543 Rev. *D
Page 15 of 17
[+] Feedback
CY14E064L
Ordering Information
Speed (ns) 25 25 35 35 45 45 Ordering Code CY14E064L-SZ25XCT CY14E064L-SZ25XC CY14E064L-SZ25XIT CY14E064L-SZ25XI CY14E064L-SZ35XCT CY14E064L-SZ35XC CY14E064L-SZ35XIT CY14E064L-SZ35XI CY14E064L-SZ45XCT CY14E064L-SZ45XC CY14E064L-SZ45XIT CY14E064L-SZ45XI Package Diagram 001-10395 001-10395 001-10395 001-10395 001-10395 001-10395 001-10395 001-10395 001-10395 001-10395 001-10395 001-10395 Package Type Operating Range
28-pin SOIC (Pb-Free) Commercial 28-pin SOIC (Pb-Free) 28-pin SOIC (Pb-Free) Industrial 28-pin SOIC (Pb-Free) 28-pin SOIC (Pb-Free) Commercial 28-pin SOIC (Pb-Free) 28-pin SOIC (Pb-Free) Industrial 28-pin SOIC (Pb-Free) 28-pin SOIC (Pb-Free) Commercial 28-pin SOIC (Pb-Free) 28-pin SOIC (Pb-Free) Industrial 28-pin SOIC (Pb-Free)
Package Diagrams
28-Pin (350 Mil) SOIC(001-10395)
001-10395-**
Document Number: 001-06543 Rev. *D
Page 16 of 17
[+] Feedback
CY14E064L
Document History Page
Document Title: CY14E064L 64 Kbit (8K x 8) nvSRAM Document Number: 001-06543 REV. ** *A *B *C ECN NO. 427789 437321 472053 503290 Issue Date See ECN See ECN See ECN See ECN Orig. of Change TUP TUP TUP PCI New datasheet Show datasheet on Web Removed 55 ns Speed Option Updated Part Numbering Nomenclature and Ordering Information Changed from Advance to Preliminary Changed the term "Unlimited" to "Infinite" Removed Industrial Grade mention Removed 35 ns speed bin Removed Icc1 values from the DC table for 35 ns Industrial Grade Corrected VIL min specification from (VCC - 0.5) to (VSS - 0.5) Removed all references pertaining to OE controlled Software STORE and RECALL operation Included Package Diagram for 28-pin (350 mil) SOIC Updated "Part Nomenclature Table" and "Ordering Information Table" Changed from Preliminary to Final Updated AC Test Conditions Updated Ordering Information Table Description of Change
*D
1349963
See ECN
UHA/SFV
(c) Cypress Semiconductor Corporation, 2007. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress' product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 001-06543 Rev. *D
Revised August 7, 2007
Page 17 of 17
PSoC DesignerTM, Programmable System-on-ChipTM, and PSoC ExpressTM are trademarks and PSoC(R) is a registered trademark of Cypress Semiconductor Corp. All other trademarks or registered trademarks referenced herein are property of the respective corporations. Purchase of I2C components from Cypress or one of its sublicensed Associated Companies conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. AutoStore and QuantumTrap are registered trademarks of Simtek Corporation. All products and company names mentioned in this document may be the trademarks of their respective holders.
[+] Feedback

▲Up To Search▲

Price & Availability of CY14E064L-SZ25XC

	To Download CY14E064L-SZ25XC Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .